资 源 简 介
1.1 Integer Unit User Programming Model 1-21.1.1 Data Registers (D7 – D0) . . 1-21.1.2 Address Registers (A7 – A0) 1-21.1.3 Program Counter 1-31.1.4 Condition Code Register 1-31.2 Floating-Point Unit User Programming Model . 1-41.2.1 Floating-Point Data Registers (FP7 – FP0) . . 1-41.2.2 Floating-Point Control Register (FPCR) 1-51.2.2.1 Exception Enable Byte 1-51.2.2.2 Mode Control Byte 1-51.2.3 Floating-Point Status Register (FPSR) . 1-51.2.3.1 Floating-Point Condition Code Byte. . 1-51.2.3.2 Quotient Byte1-61.2.3.3 Exception Status Byte . 1-61.2.3.4 Accrued Exception Byte . . 1-71.2.4 Floating-Point Instruction Address Register (FPIAR) . 1-81.3 Supervisor Programming Model . . 1-81.3.1 Address Register 7 (A7) . . 1-101.3.2 Status Register 1-101.3.3 Vector Base Register (VBR) . . 1-111.3.4 Alternate Function Code Registers (SFC and DFC) . 1-111.3.5 Acu Status Register (MC68EC030 only) 1-111.3.6 Transparent Translation/access Control Registers . . 1-121.3.6.1 Transparent Translation/access Control Register Fields for theM680301-121.3.6.2 Transparent Translation/access Control Register Fields for theM680401-131.4 Integer Data Formats 1-141.5 Floating-Point Data Formats 1-151.5.1 Packed Decimal Real Format . 1-151.5.2 Binary Floating-Point Formats . 1-161.6 Floating-Point Data Types . . 1-171.6.1 Normalized Numbers . . 1-181.6.2 Denormalized Numbers 1-181.6.3 Zeros 1-191.6.4 Infinities . 1-191.6.5 Not-A-Numbers 1-191.6.6 Data Format and Type Summary . 1-201.7 Organization of Data in Registers . . 1-251.7.1 Organization of Integer Data Formats in Registers . . 1-251.7.2 Organization of Integer Data Formats in Memory 1-271.7.3 Organization of Fpu Data Formats in Registers and Memory 1-30Section 2Addressing Capabilities2.1 Instruction Format 2-12.2 Effective Addressing Modes . . 2-42.2.1 Data Register Direct Mode . 2-52.2.2 Address Register Direct Mode . . 2-52.2.3 Address Register Indirect Mode 2-52.2.4 Address Register Indirect with Postincrement Mode . . 2-62.2.5 Address Register Indirect with Predecrement Mode . . 2-72.2.6 Address Register Indirect with Displacement Mode . . 2-82.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode . 2-92.2.8 Address Register Indirect with Index (Base Displacement) Mode 2-102.2.9 Memory Indirect Postindexed Mode . . 2-112.2.10 Memory Indirect Preindexed Mode 2-122.2.11 Program Counter Indirect with Displacement Mode . 2-132.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode 2-142.2.13 Program Counter Indirect with Index (Base Displacement) Mode 2-152.2.14 Program Counter Memory Indirect Postindexed Mode . . 2-162.2.15 Program Counter Memory Indirect Preindexed Mode 2-172.2.16 Absolute Short Addressing Mode . 2-182.2.17 Absolute Long Addressing Mode . . 2-182.2.18 Immediate Data 2-192.3 Effective Addressing Mode Summary . . 2-192.4 Brief Extension Word Format Compatibility . . 2-212.5 Full Extension Addressing Modes . . 2-222.5.1 No Memory Indirect Action Mode . 2-242.5.2 Memory Indirect Modes 2-252.5.2.1 Memory Indirect with Preindex . . 2-252.5.2.2 Memory Indirect with Postindex . 2-262.5.2.3 Memory Indirect with Index Suppressed.. 2-272.6 Other Data Structures . . 2-282.6.1 System Stack. 2-282.6.2 Queues . 2-29Section 3Instruction Set Summary3.1 Instruction Summary . 3-13.1.1 Data Movement Instructions 3-53.1.2 Integer Arithmetic Instructions . . 3-63.1.3 Logical Instructions . 3-83.1.4 Shift and Rotate Instructions 3-83.1.5 Bit Manipulation Instructions . . 3-103.1.6 Bit Field Instructions . . 3-103.1.7 Binary-Coded Decimal Instructions 3-113.1.8 Program Control Instructions . . 3-113.1.9 System Control Instructions 3-123.1.10 Cache Control Instructions (MC68040) 3-143.1.11 Multiprocessor Instructions 3-143.1.12 Memory Management Unit (MMU) Instructions . . 3-153.1.13 Floating-Point Arithmetic Instructions . 3-153.2 Integer Unit Condition Code Computation 3-173.3 Instruction Examples 3-203.3.1 Using the Cas and Cas2 Instructions . 3-203.3.2 Using the Moves Instruction . . 3-203.3.3 Nested Subroutine Calls . . 3-203.3.4 Bit Field Instructions . . 3-203.3.5 Pipeline Synchronization with the Nop Instruction 3-213.4 Floating-Point Instruction Details 3-213.5 Floating-Point Computational Accuracy . 3-233.5.1 Intermediate Result 3-243.5.2 Rounding the Result . . 3-253.6 Floating-Point Postprocessing . . 3-273.6.1 Underflow, Round, Overflow . . 3-283.6.2 Conditional Testing 3-283.7 Instruction Descriptions . 3-328.1.1 Coprocessor ID Field 8-18.1.2 Effective Address Field . 8-18.1.3 Register/Memory Field . 8-18.1.4 Source Specifier Field . . 8-18.1.5 Destination Register Field . . 8-28.1.6 Conditional Predicate Field . 8-28.1.7 Shift and Rotate Instructions 8-28.1.7.1 Count Register Field . . 8-28.1.7.2 Register Field8-28.1.8 Size Field. 8-48.1.9 Opmode Field . 8-48.1.10 Address/Data Field . 8-48.2 Operation Code Map . 8-4Appendix AProcessor Instruction SummaryA.1 MC68000, MC68008, MC68010 Processors . A-12A.1.1 M68000, MC68008, and MC68010 Instruction Set . . A-12A.1.2 MC68000, MC68008, and MC68010 Addressing Modes A-16A.2 MC68020 Processors A-17A.2.1 MC68020 Instruction Set . . A-17A.2.2 MC68020 Addressing Modes . A-20A.3 MC68030 Processors A-21A.3.1 MC68030 Instruction Set . . A-21A.3.2 MC68030 Addressing Modes . A-24A.4 MC68040 Processors A-25A.4.1 MC68040 Instruction Set . . A-25A.4.2 MC68040 Addressing Modes . A-29A.5 MC68881/MC68882 Coprocessors . A-30A.5.1 MC68881/MC68882 Instruction Set . . A-30A.5.2 MC68881/MC68882 Addressing Modes A-31A.6 MC68851 Coprocessors . A-31A.6.1 MC68851 Instruction Set . . A-31A.6.2 MC68851 Addressing Modes . A-31C.1 S-Record ContentC-1C.2 S-Record Types . C-2C.3 S-Record Creation C-31-1 M68000 Family User Programming Model 1-21-2 M68000 Family Floating-Point Unit User Programming Model....... 1-41-3 Floating-Point Control Register ....... 1-51-4 FPSR Condition Code Byte 1-61-5 FPSR Quotient Code Byte . 1-61-6 FPSR Exception Status Byte .......... 1-61-7 FPSR Accrued Exception Byte ....... 1-71-8 Status Register 1-111-9 MC68030 Transparent Translation/MC68EC030 AccessControl Register Format... 1-121-10 MC68040 and MC68LC040 Transparent Translation/MC68EC040Access Control Register Format ... 1-131-11 Packed Decimal Real Format ....... 1-161-12 Binary Floating-Point Data Formats ........ 1-161-13 Normalized Number Format.......... 1-181-14 Denormalized Number Format...... 1-181-15 Zero Format .... 1-191-16 Infinity Format . 1-191-17 Not-A-Number Format...... 1-191-19 Organization of Integer Data Formats in Address Registers......... 1-261-18 Organization of Integer Data Formats in Data Registers .............. 1-261-20 Memory Operand Addressing ....... 1-271-21 Memory Organization for Integer Operands 1-291-22 Organization of FPU Data Formats in Memory............ 1-302-1 Instruction Word General Format.... 2-12-2 Instruction Word Specification Formats .... 2-22-3 M68000 Family Brief Extension Word Formats............ 2-212-4 Addressing Array Items.... 2-232-5 No Memory Indirect Action............ 2-242-6 Memory Indirect with Preindex...... 2-262-7 Memory Indirect with Postindex ... 2-272-8 Memory Indirect with Index Suppress.... 2-273-1 Intermediate Result Format........... 3-243-2 Rounding Algorithm Flowchart...... 3-263-3 Instruction Description Format ...... 3-33B-1 MC68000 Group 1 and 2 Exception Stack Frame .........B-3B-2 MC68000 Bus or Address Error Exception Stack Frame................B-3B-3 Four-Word Stack Frame, Format $0 .........B-3B-4 Throwaway Four-Word Stack Frame, Format $1...........B-3B-5 Six-Word Stack Frame, Format $2..B-4B-6 MC68040 Floating-Point Post-Instruction Stack Frame, Format $3B-4B-7 MC68EC040 and MC68LC040 Floating-Point UnimplementedStack Frame, Format $4 ....B-5B-8 MC68040 Access Error Stack Frame, Format $7 .........B-5B-9 MC68010 Bus and Address Error Stack Frame, Format $8 ..........B-6B-10 MC68020 Bus and MC68030 Coprocessor Mid-InstructionStack Frame, Format $9 ....B-6B-11 MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A...............B-7B-12 MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B...............B-8B-13 CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C.....B-8B-14 CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C B-9B-15 CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C...B-9B-16 MC68881/MC68882 and MC68040 Null Stack FrameB-10B-17 MC68881 Idle Stack Frame .........B-10B-18 MC68881 Busy Stack Frame .......B-11B-19 MC68882 Idle Stack Frame ..........B-11B-20 MC68882 Busy Stack Frame ........B-11B-21 MC68040 Idle Busy Stack Frame .B-12B-22 MC68040 Unimplimented Instruction Stack Frame......B-12B-23 MC68040 Busy Stack Frame ........B-13C-1 Five Fields of an S-Record.C-1C-2 Transmission of an S1 Record........C-41-1 Supervisor Registers Not Related To Paged Memory Management .............. 1-91-2 Supervisor Registers Related To Paged Memory Management.. 1-101-3 Integer Data Formats ...... 1-151-4 Single-Precision Real Format Summary Data Format 1-211-5 Double-Precision Real Format Summary... 1-221-6 Extended-Precision Real Format Summary................ 1-231-6 Extended-Precision Real Format Summary (Continued)............. 1-241-7 Packed Decimal Real Format Summary 1-241-8 MC68040 FPU Data Formats and Data Types ........... 1-302-1 Instruction Word Format Field Definitions 2-32-2 IS-I/IS Memory Indirect Action Encodings 2-42-3 Immediate Operand Location....... 2-192-4 Effective Addressing Modes and Categories .............. 2-203-1 Notational Conventions ..... 3-23-1 Notational Conventions (Continued) ........ 3-33-1 Notational Conventions (Concluded) ....... 3-43-2 Data Movement Operation Format. 3-63-3 Integer Arithmetic Operation Format........ 3-73-4 Logical Operation Format.. 3-83-5 Shift and Rotate Operation Format 3-93-6 Bit Manipulation Operation Format ........ 3-103-7 Bit Field Operation Format ........... 3-103-8 Binary-Coded Decimal Operation Format.. 3-113-9 Program Control Operation Format........ 3-123-10 System Control Operation Format ......... 3-133-11 Cache Control Operation Format. 3-143-12 Multiprocessor Operations ........... 3-143-13 MMU Operation Format .. 3-153-14 Dyadic Floating-Point Operation Format 3-163-15 Dyadic Floating-Point Operations 3-163-16 Monadic Floating-Point Operation Format . 3-163-17 Monadic Floating-Point Operations........ 3-173-18 Integer Unit Condition Code Computations 3-183-19 Conditional Tests ............ 3-193-20 Operation Table Example (FADD Instruction)............. 3-223-21 FPCR Encodings............. 3-253-22 FPCC Encodings............. 3-293-23 Floating-Point Conditional Tests .. 3-315-1 Directly Supported Floating-Point Instructions .............. 5-25-2 Indirectly Supported Floating-Point Instructions............ 5-37-1 MC68020 Instructions Not Supported...... 7-17-2 M68000 Family Addressing Modes 7-27-3 CPU32 Instruction Set....... 7-38-1 Conditional Predicate Field Encoding ...... 8-38-2 Operation Code Map......... 8-4A-1 M68000 Family Instruction Set And Processor Cross-Reference..A-1A-2 M68000 Family Instruction Set.......A-8A-3 MC68000 and MC68008 Instruction SetA-12A-4 MC68010 Instruction Set.A-14A-5 MC68000, MC68008, and MC68010 Data Addressing Modes....A-16A-6 MC68020 Instruction Set Summary .......A-17A-7 MC68020 Data Addressing Modes ........A-20A-8 MC68030 Instruction Set Summary .......A-21A-9 MC68030 Data Addressing Modes ........A-24A-10 MC68040 Instruction Set.A-25A-11 MC68040 Data Addressing Modes ........A-29A-12 MC68881/MC68882 Instruction Set.......A-30A-13 MC68851 Instruction Set.A-31B-1 Exception Vector Assignments for the M68000 Family.B-2C-1 Field Composition of an S-Record .C-1C-2 ASCII Code ......C-5
