资 源 简 介
The DS90CR481 transmitter converts 48 bits of CMOS/TTLdata into eight LVDS (Low Voltage DifferenTIal Signaling)data streams. A phase-locked transmit clock is transmitted inparallel with the data streams over a ninth LVDS link. Everycycle of the transmit clock 48 bits of input data are sampledand transmitted. The DS90CR482 receiver converts theLVDS data streams back into 48 bits of LVCMOS/TTL data.At a transmit clock frequency of 112MHz, 48 bits of TTL dataare transmitted at a rate of 672Mbps per LVDS data channel.Using a 112MHz clock, the data throughput is 5.38Gbit/s(672Mbytes/s). At a transmit clock frequency of 112MHz, 48bits of TTL data are transmitted at a rate of 672Mbps perLVDS data channel. Using a 66MHz clock, the data throughputis 3.168Gbit/s (396Mbytes/s).
