首页| 行业标准| 论文文档| 电子资料| 图纸模型
购买积分 购买会员 激活码充值

您现在的位置是:团子下载站 > 其他 > DDR2_DDR3_SDRAM,PCB布线规则指导

DDR2_DDR3_SDRAM,PCB布线规则指导

  • 资源大小:0.54 MB
  • 上传时间:2021-12-24
  • 下载次数:0次
  • 浏览次数:24次
  • 资源积分:1积分
  • 标      签: SDRAM pcb

资 源 简 介

DDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently,   1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementaTIon standpoint, a primary   requirement is delay matching which is dictated by the TIming requirement. This brings into it a number of related   factors that affect waveform integrity and delay. These factors are interdependent, but where a disTIncTIon can   be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross   talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.
VIP VIP