On-Chip ESD Protection for Int

The author first got in touch with the ESD things in late 1996 when hewas a Staff R&D Engineer at the NaTIonal Semiconductor CorporaTIon,where he was assigned by the boss to develop some on-chip ESD protecTIoncircuits for mixed-signal IC chips. Ever since then, the not-so-attracTIve ESDprotection circuit design topics have been on and off the author’s table bothat the company’s cubicle and in the office at the Illinois Institute ofTechnology, where the author joined its faculty team of Electrical andComputer Engineering in Fall 1998. Exactly like all the other IC designers,the author does not really like the little ESD thing and has no fun in doingESD protection circuit design. Unfortunately, life is life. One has to dealwith some unpleasant issues sometime somewhere somehow. The harshreality is that an IC designer must find the right ESD protection solution forthe IC chips. If there is no ESD protection provided, nobody will buy yourchips. If there is no sufficient ESD protection for your chips, you will losethe market to your competitors. Period! What makes an IC designer’s lifeeven more miserable is the fact that as IC technologies advance, thecustomer demands for IC ESD robustness and the complexity of on-chipESD protection circuit design increase dramatically, as evidenced by thehuge amount of related papers published in the past decade. Whilesignificant progresses have been made in the field of ESD protectionresearch and design, IC designers are deeply bothered by the situation thatthere are too much qualitative sayings and too few quantitative analyses onthe ESD protection design matters. Hence, very little success in predictingESD protection circuit design is expected. One question commonly heard inthe IC circuit design community is that “how do I design the ESD protectionfor my chips, with prediction, as a circuit designer?” This book tries toprovide the information necessary to address this tough design challengefrom an IC circuit designer’s angle.