资 源 简 介
These 12-bit buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The 3-state control gate is a 2-input AND gate with acTIve-low inputs so that if either output-enable ( or) input is high, all 12 outputs are in the high-impedance state. These devices provide inverted data.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, should be TIed to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
