资 源 简 介
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operaTIon.
Data flow in each direcTIon is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input.
Data is stored in the internal registers on the low-to-high transiTIon of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK.
To ensure the high-impedance state during power up or power down, OE should be TIed to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
