资 源 简 介
The CD4035B 4-bit parallel-in/parallel-out shift register is amonolithic complementary MOS (CMOS) integrated circuitconstructed with P- and N-channel enhancement modetransistors. This shift register is a 4-stage clocked serial registerhaving provisions for synchronous parallel inputs toeach stage and serial inputs to the first stage via JK logic.Register stages 2, 3, and 4 are coupled in a serial ``D' flipflopconfiguration when the register is in the serial mode(parallel/serial control low).Parallel entry via the ``D' line of each register stage is permittedonly when the parallel/serial control is ``high'.In the parallel or serial mode, information is transferred onpositive clock transitions.When the true/complement control is ``high', the true contentsof the register are available at the output terminals.When the true/complement control is ``low', the outputs arethe complements of the data in the register. The true/complementcontrol functions asynchronously with respect tothe clock signal.
JK input logic is provided on the first stage serial input tominimize logic requirements particularly in counting and sequence-generation applications. With JK inputs connectedtogether, the first stage becomes a ``D' flip-flop. An asynchronouscommon reset is also provided.
