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The device is a Low-power applicaTIons processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operaTIng systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor soluTIon.
The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associaTIve cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space.
