资 源 简 介
Chapter 1: IntroducTIon to SystemVerilogChapter 2: SystemVerilog DeclaraTIon SpacesExample 2-1: A package definiTIon ...9Example 2-2: Explicit package references using the :: scope resoluTIon operator .10Example 2-3: Importing specific package items into a module 11Example 2-4: Using a package wildcard import 13Example 2-5: External declarations in the compilation-unit scope (not synthesizable) 15Example 2-6: Package with conditional compilation (file name: definitions.pkg) 21Example 2-7: A design file that includes the conditionally-compiled package file 23Example 2-8: A testbench file that includes the conditionally-compiled package file .23Example 2-9: Mixed declarations of time units and precision (not synthesizable) 34Chapter 3: SystemVerilog Literal Values and Built-in Data TypesExample 3-1: Relaxed usage of variables 53Example 3-2: Illegal use of variables ..54Example 3-3: Applying reset at simulation time zero with 2-state types 65Chapter 4: SystemVerilog User-Defined and Enumerated TypesExample 4-1: Directly referencing typedef definitions from a package ..77Example 4-2: Importing package typedef definitions into $unit ...78Example 4-3: State machine modeled with Verilog ‘define and parameter constants 79Example 4-4: State machine modeled with enumerated types .81Example 4-5: Using special methods to iterate through enumerated type lists ..91Example 4-6: Printing enumerated types by value and by name ...92Chapter 5: SystemVerilog Arrays, Structures and UnionsExample 5-1: Using structures and unions ..112Example 5-2: Using arrays of structures to model an instruction register ..129Chapter 6: SystemVerilog Procedural Blocks, Tasks and FunctionsExample 6-1: A state machine modeled with always procedural blocks 145Example 6-2: A state machine modeled with always_comb procedural blocks ...147Example 6-3: Latched input pulse using an always_latch procedural block 151Chapter 7: SystemVerilog Procedural StatementsExample 7-1: Using SystemVerilog assignment operators 175Example 7-2: Code snippet with unnamed nested begin...end blocks ...192Example 7-3: Code snippet with named begin and named end blocks ..193Chapter 8: Modeling Finite State Machines with SystemVerilogExample 8-1: A finite state machine modeled with enumerated types (poor style) ..208Example 8-2: Specifying one-hot encoding with enumerated types .210Example 8-3: One-hot encoding with reversed case statement style .212Example 8-4: Code snippet with illegal assignments to enumerated types 216Chapter 9: SystemVerilog Design HierarchyExample 9-1: Nested module declarations ..228Example 9-2: Hierarchy trees with nested modules 231Example 9-3: Simple netlist using Verilog’s named port connections ..235Example 9-4: Simple netlist using SystemVerilog’s .name port connections 239Example 9-5: Simple netlist using SystemVerilog’s .* port connections .243Example 9-6: Netlist using SystemVerilog’s .* port connections without aliases ..248Example 9-7: Netlist using SystemVerilog’s .* connections along with net aliases .249Example 9-8: Passing structures and arrays through module ports ...252Example 9-9: Passing a reference to an array through a module ref port ...255Example 9-10: Polymorphic adder using parameterized variable types ..261Chapter 10: SystemVerilog InterfacesExample 10-1: Verilog module interconnections for a simple design .264Example 10-2: SystemVerilog module interconnections using interfaces ...270Example 10-3: The interface definition for main_bus, with external inputs ..274Example 10-4: Using interfaces with .* connections to simplify complex netlists ..275Example 10-5: Referencing signals within an interface .280Example 10-6: Selecting which modport to use at the module instance .283Example 10-7: Selecting which modport to use at the module definition 284Example 10-8: A simple design using an interface with modports .287Example 10-9: Using modports to select alternate methods within an interface 291Example 10-10:Exporting a function from a module through an interface modport ...294Example 10-11:Exporting a function from a module into an interface 294Example 10-12:Using parameters in an interface ...297Chapter 11: A Complete Design Modeled with SystemVerilogExample 11-1: Utopia ATM interface, modeled as a SystemVerilog interface .306Example 11-2: Cell rewriting and forwarding configuration ...307Example 11-3: ATM squat top-level module 309Example 11-4: Utopia ATM receiver ..315Example 11-5: Utopia ATM transmitter ..318Example 11-6: UtopiaMethod interface for encapsulating test methods .321Example 11-7: CPUMethod interface for encapsulating test methods 322Example 11-8: Utopia ATM testbench 323Chapter 12: Behavioral and Transaction Level ModelingExample 12-1: Simple memory subsystem with read and write tasks 333Example 12-2: Two memory subsystems connected by an interface ..335Example 12-3: TLM model with bus arbitration using semaphores ...338Example 12-4: Adapter modeled as a module ...341Example 12-5: Simplified Intel Multibus with multiple masters and slaves 342Example 12-6: Simple Multibus TLM example with master adapter as a module 343Example 12-7: Simple Multibus TLM example with master adapter as an interface .348
