资 源 简 介
These 4-bit bidirecTIonal universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operaTIng-mode-control (S0, S1) inputs, and a direct overriding clear (CLR) line. The registers have four disTInct modes of operaTIon:
Inhibit clock (temporary data latch/do nothing)
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Parallel (broadside) load
Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.
