资 源 简 介
DescripTIon STM6502 has two combined Smart Reset inputs （SR0 and SR1） with delayed Smart Reset setup TIme （tSRC） programmed by an external capacitor on the SRC pin. STM6503 is similar to STM6502， has two combined delayed Smart Reset inputs （SR0， SR1） and three user-selectable delayed Smart Reset setup TIme （tSRC） opTIons of 2 s， 6 s and 10 s through a three-state TSR input pin： when connected to ground， tSRC = 2 s; when left open， tSRC = 6 s; when connected to VCC， tSRC = 10 s （all the times are minimum）。 STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset setup time （tSRC） function with three user-selectable tSRC options through a three-state TSR input pin： when connected to ground， tSRC = 2 s; when left open， tSRC = 6 s; when connected to VCC， tSRC = 10 s （all the times are minimum）。 SRE provides instant reset. SRE is edge-triggered with a special debounce time （tDEBOUNCE = 240 ms min.） at the falling edge after a valid reset period. STM6505 has two combined delayed Smart Reset inputs （SR0， SR1） and provides an adjustable reset delay setup time via an external capacitor connected to the SRC pin. The RST output depends also on the VCC monitoring threshold. STM6505 also provides independent low battery detect （BLD） output controlled by the secondary external input voltage VBAT. VBAT is monitored for low voltage and provides an indication on the battery low detect output pin （BLD）。 VBAT threshold is 1.25 V， fixed， and an external resistor divider is to be used to set the actual battery voltage threshold. VBAT threshold hysteresis is 8 mV typ. （16 mV max.）。 VBAT is voltage monitoring input only， the device is powered only from the VCC pin; VCC must be ≥ 1.575 V for proper operation of the VBAT comparator.
