RTL8305SB pdf,datasheet (REALT

2. General DescripTIon 33. Block Diagram44. Pin Assignments 55. Pin DescripTIons.75.1 Media ConnecTIon Pins ..75.2 ConfiguraTIon Pins 75.3 Port4 External MAC Interface Pins..85.4 Miscellaneous Pins.135.5 Per Port LED Pins ..145.6 Power Pins..155.7 Reserved Pins 165.8 Serial EEPROM and SMI Pins.165.9 Strapping Pins ..175.10 Port Status Strapping Pins 196. Register Description.216.1 PHY0 to 4: PHY Register of Each Port226.1.1 Register0: Control Register .226.1.2 Register1: Status Register.236.1.3 Register4: Auto-Negotiation Advertisement Register..236.1.4 Register5: Auto-Negotiation Link Partner Ability Register..246.1.5 Register6: Auto-Negotiation Expansion Register.246.2 PHY0: EEPROM Register0 ..256.2.1 Register16: EEPROM Byte0 and 1 Register ..256.2.2 Register17: EEPROM Byte2 and 3 Register ..256.2.3 Register18~20: EEPROM EthernetID Register.256.2.4 Register21: EEPROM Byte10 and 11 Register .266.2.5 Register22: EEPROM Byte12 and 13 Register .266.3 PHY1: EEPROM Register1 ..276.3.1 Register16~23: EEPROM (Byte 14~29) Register276.3.2 Register24~31: EEPROM VLAN (Byte 30~44) Register.276.4 PHY2: Pin & EEPROM Register286.4.1 Register16: Pin Register 286.4.2 Register17: Pin & EEPROM Register for VLAN296.5 PHY3: Port Control Register.306.5.1 Register16: Port Control Register.306.5.2 Register17: EEPROM (Byte 46) Register 316.5.3 Register18~20: EEPROM (Byte 47~52) Register317. Functional Description ..327.1 Switch Core Functional Overview .327.1.1 Application ..327.1.2 Port4 327.1.3 Port Status Configuration .367.1.4 Enable Port ..367.1.5 Flow Control377.1.6 Address Search, Learning and Aging .387.1.7 Address Direct Mapping Mode..387.1.8 Half Duplex Operation ..387.1.9 Inter-Frame Gap 387.1.10 Illegal Frame.387.2 Physical Layer Functional Overview .. 397.2.1 Auto-Negotiation for UTP.. 397.2.2 10Base-T Transmit Function . 397.2.3 10Base-T Receive Function 397.2.4 Link Monitor.. 397.2.5 100Base-TX Transmit Function 397.2.6 100Base-TX Receive Function . 397.2.7 100Base-FX 397.2.8 100Base-FX Transmit Function 407.2.9 100Base-FX Receive Function . 407.2.10 100Base-FX Far-End-Fault-Indication (FEFI) 407.2.11 Reduced Fiber Interface . 407.2.12 Power Saving Mode. 407.2.13 Reg0.11 Power Down Mode 407.2.14 Crossover Detection and Auto Correction  417.2.15 Polarity Detection and Correction. 417.3 Advanced Functional Overview. 427.3.1 Reset .. 427.3.2 Setup and Configuration .. 427.3.3 Example of Serial EEPROM: 24LC02 . 437.3.4 24LC02 Device Operation .. 437.3.5 SMI . 447.3.6 Head-Of-Line Blocking  447.3.7 802.1Q Port Based VLAN.. 447.3.8 QoS Function . 467.3.9 Insert/Remove VLAN Priority Tag. 467.3.10 Filtering/Forwarding Reserved Control Frame477.3.11 Broadcast Storm Control 477.3.12 Broadcast In/Out Drop 477.3.13 Loop Detection .. 487.3.14 MAC Loopback return to External .. 497.3.15 Reg0.14 PHY Loopback return to Internal .. 507.3.16 LED . 507.3.17 2.5V Power Generation.. 527.3.18 Crystal/Oscillator .. 528. Serial EEPROM Description. 539. Electrical Characteristics  579.1 Absolute Maximum Ratings: 579.2 Operating Range: 579.3 DC Characteristics. 579.4 AC Characteristics. 589.5 Digital Timing Characteristics. 599.6 Thermal Data 5910. Application Information  6010.1 UTP (10Base-T/100Base-TX) Application  6010.2 100Base-FX Application: 6211. System Application Diagram.. 6312. Design and Layout Guide . 6413. Mechanical Dimensions . 65