The Verilog Hardware Descripti

The Verilog language is a hardware description language that provides a means ofspecifying a digital system at a wide range of levels of abstraction. The language supportsthe early conceptual stages of design with its behavioral level of abstraction, andthe later implementation stages with its structural abstractions. The language includeshierarchical constructs, allowing the designer to control a description’s complexity.Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Later, several other proprietary analysis tools were developedaround the language, including a fault simulator and a timing analyzer. More recently,Verilog has also provided the input specification for logic and behavioral synthesistools. The Verilog language has been instrumental in providing consistency acrossthese tools. The language was originally standardized as IEEE standard #1364-1995.It has recently been revised and standardized as IEEE standard #1364-2001. Thisbook presents this latest revision of the language, providing material for the beginningstudent and advanced user of the language.It is sometimes difficult to separate the language from the simulator tool becausethe dynamic aspects of the language are defined by the way the simulator works. Further,it is difficult to separate it from a synthesis tool because the semantics of the languagebecome limited by what a synthesis tool allows in its input specification andproduces as an implementation. Where possible, we have stayed away from simulatorandsynthesis-specific details and concentrated on design specification. But, we haveincluded enough information to be able to write working executable models. Verilog –A Tutorial Introduction 1Getting StartedA Structural DescriptionSimulating the binaryToESeg DriverCreating Ports For the ModuleCreating a Testbench For a ModuleBehavioral Modeling of Combinational CircuitsProcedural ModelsRules for Synthesizing Combinational CircuitsProcedural Modeling of Clocked Sequential CircuitsModeling Finite State MachinesRules for Synthesizing Sequential SystemsNon-Blocking Assignment ("<=")Module HierarchyThe CounterA Clock for the SystemTying the Whole Circuit TogetherTying Behavioral and Structural Models Together