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A CPLD VHDL Introduction
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundly to CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.
VHDL, an extremely versatile tool developed to aid in many aspects of IC design, allows a userto structure circuits in many levels of detail. This versatility also makes the job of the VHDLsynthesis tool a lot more complex, and there is latitude for interpretation depending on theVHDL coding style. One synthesis tool may implement the same code very differently fromanother. In order to achieve the best results using VHDL, the designer should work at theRegister Transfer Level (RTL).Although working at the RTL for designs may be more time-consuming, all major synthesistools on the market are capable of generating a clear cut implementation of designs for CPLDsat this level. Using higher levels of abstraction may give adequate results, but tend to be lessefficient. Additionally, by expressing designs in this manner, the designer also gains the abilityto port VHDL designs from one synthesis tool to another with minimal effort. The followingexamples will show designers the best design practices when targeting Xilinx XC9500XL,XC9500XV and CoolRunnerTM XPLA3 families.This application note covers the following topics:
