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1.0 INTRODUCTION 12.0 MEMORY ORGANIZATION 22.1 Program Memory 22.2 Data Memory 23.0 SPECIAL FUNCTIONREGISTERS 44.0 PORT STRUCTURES ANDOPERATION 104.1 I/O Configurations 104.2 Port 1 and Port 3 104.3 Port 0 and Port 2 104.4 Read-Modify-Write Instructions 134.5 Quasi-Bidirectional PortOperation 134.6 Port Loading 144.7 Accessing External Memory 154.7.1 Bus Cycle Definition 174.7.2 External Bus Cycles with WaitStates 214.7.3 Port 0 and Port 2 for States inNon-Page and Page Mode 225.0 TIMERS/COUNTERS 235.1 TIMER 0 AND TIMER 1 235.2 TIMER 2 266.0 PROGRAMMABLE COUNTERARRAY 306.1 PCA 16-Bit Timer/Counter 326.2 Capture/Compare Modules 346.3 16-Bit Capture Mode 376.4 16-Bit Software Timer Mode 376.5 High Speed Output Mode 386.6 Watchdog Timer Mode 386.7 Pulse Width Modulator Mode 397.0 SERIAL INTERFACE 417.1 Framing Error Detection 427.2 Multiprocessor Communications 427.3 Automatic Address Recognition 427.4 Baud Rates 447.5 Using Timer 1 to Generate BaudRates 447.6 Using Timer 2 to Generate BaudRates 458.0 WATCHDOG TIMER 468.1 Using the WDT 468.2 WDT during Idle Mode andPowerdown 469.0 INTERRUPTS 479.1 External Interrupts 479.2 Timer Interrupts 499.3 PCA Interrupt 509.4 Serial Port Interrupt 509.5 Interrupt Enable 509.6 Interrupt Priorities 519.7 Interrupt Processing 549.7.1 Minimum Fixed InterruptTime 559.7.2 Variable InterruptParameter 559.7.3 Response Time Variables 559.7.4 Computation of Worst-CaseLatency With Variables 569.7.5 Blocking Conditions 579.7.6 Interrupt Vector Cycle 579.7.7 ISRs in Process 5810.0 RESET 5810.1 Externally Initiated Resets 5810.2 WDT Initiated Resets 5910.3 Reset Operation 5910.4 Power-on Reset 5911.0 POWER-SAVING MODES OFOPERATION 6011.1 Idle Mode 6012.0 PROGRAMMING AND VERIFYINGNONVOLATILE MEMORY 6212.1 Programming and VerifyingModes 6212.2 Lock Bit System 6412.3 Encryption Array 6412.4 Signature Bytes 6413.0 ON-CIRCUIT EMULATION (ONCE)MODE 6514.0 ON-CHIP OSCILLATOR 6615.0 INSTRUCTION SETREFERENCE 68
