Parasitic-Aware Optimization o

ParasiTIc-Aware OpTImizaTIon of CMOS RF Circuits:In the near future, people’s daily acTIvities will be dominated withportable wireless devices. To make compact and energy efficient mobilecommunicating equipment such as mobile phones, wireless modems, twowayradios, etc., integrated circuit technology (IC) is necessary because itnot only reduces the size, weight, and power consumption of such devices, itenables manufacturers to include greater functionality at lower costs. Figure1-1 shows a general system-on-chip (SOC) solution that comprises digital,analog, micro-electro-mechanical systems (MEMS), and radio frequency(RF) circuit blocks. By implementing a sensor in conjunction with an RFfront end, the SOC can receive or transmit data from external sources. Thedigital circuitry on the chip consists of CPU, DSP, and memory blocks, andis used for data processing. Analog-to-digital converters (ADC) and digitalto-analog converters (DAC) enable the communication of informationbetween the digital and analog circuits.It was not long ago that all RF circuits were implemented using galliumarsenide (GaAs) or bipolar junction transistor (BJT) technologies. CMOStechnology was not viable due to its low values of breakdown voltage,small-signal transconductance, and unity current gain frequencyMoreover, the lossy silicon substrates contributed a plethora of parasiticelements to the monolithic passive components that made CMOS inferior toits bipolar and GaAs counterparts.However, because CMOS has dominated the world of digital ICs formore than a quarter century and has achieved a very high level of integration, it has become an extremely compelling and cost effective option for use inSOC design [1],[2]. It has been shown that mixed-signal functions such asADCs are effectively designed in CMOS [3],[4]. But despite a large numberof books and other publications [5]-[7], critical RF circuitry such as lownoiseamplifiers (LNA), up- and down-conversion mixers, voltagecontrolledoscillators (VCO), power amplifiers (PA), and wide-bandamplifiers still pose difficult challenges to circuit designers. Alternativesolutions such as multi-chip modules and System-in-Package (SIP) solutionsalong with the use of the traditional GaAs technology are difficult toimplement or expensive. Thus, in order to exploit CMOS as the technologysolution for high-volume SOC design and manufacture, the inferior nature ofthe technology, especially with respect to parasitic elements, needs to beovercome. Our experience over the past several years has shown that oneway to achieve high performance designs with robust manufacturingcharacteristics vis-a-vis process, temperature, and voltage variations is toperform global optimization of CMOS RF integrated circuits by includingall device and package parasitics as part of the design process.