Unique Chips and Systems

Growing on-chip wire delays, coupled with complexity and power limitaTIons,have placed severe constraints on the issue-width scaling of centralizedsuperscalar architectures. As a result, recent microprocessor designshave backed away from powerful uniprocessors, instead favoring mulTIplesimpler cores on a single die. ParTITIoning the chip into a collection of processors communicating via a common memory system mitigates some of thetechnology scaling challenges, but increases the burden on software to providemultiple threads to execute concurrently across the cores.An alternative is to pursue more powerful uniprocessors, but design themso that they are scalable and tolerant of technology and complexity scaling.Ideally, such wide-issue processors would be tiled [30], meaning composedof multiple replicated, communicating design blocks. Because of multicyclecommunication delays across these large processors, control must be distributedacross the tiles. We advocate the use of microarchitectural networks(or micronets) for routing control and data among the tiles. Micronets providehigh-bandwidth, flow-controlled transport for control or data in a wiredominatedprocessor by connecting the multiple tiles, each of which is a client on one or more micronets. Higher-level microarchitectural protocols direct global control across themicronets and tiles in a manner invisible to software.In this chapter,we describe the architecture and implementation of the Teraop,Reliable, Intelligently-adaptive Processing System (TRIPS) processor—adistributed, tiled microarchitecture. In particular, we discuss TRIPS tile partitioning,micronet connectivity, anddistributedprotocols thatprovide globalservices in the TRIPS processor, including distributed fetch, execution, flush,and commit. Although some of our prior publications have described theTRIPS approach to exploiting parallelism as well as high-level performanceresults [20,3], this chapter examines in detail the intertile connectivity andprotocols that have resulted from reducing the high-level design to silicon.The key concepts that differentiate TRIPS from other tiled architectures suchas RAW[30] are the dynamic scheduling and execution which require distributeddynamic hardware protocols to provide the means to extract bothirregular and regular concurrency.