资 源 简 介
FPGA的有源电容放电电路考虑
介绍
在电信设备、服务器和数据中心中发现的最新FPGA有多个电源轨，需要对这些系统进行安全的上下排序。高可靠性的DC - DC稳压器和FPGA电源管理的设计者需要一个简单的方法来安全地卸下大容量电容器，以避免损坏系统。
FPGA Power Sequencing
For the latest generaTIon system-on-chip FPGAs， they can have on the order of ten separate power rails supplying the Vcore， memory bus supply， I/O controllers， Ethernet， etc. As shown in Figure 1， each rail is supplied by a DC-DC converter to regulate the required voltage supply of 3.3 V， 2.5 V， 1.8 V， 0.9 V， and more. To power up the system， a parTIcular sequence is followed to ensure safe operaTIon and avoid damaging the system. Likewise during system shutdown， the power sequence is in the reverse order， ensuring each power rail is disabled before the next is switched off. This order is controlled via a Power Sequencer chip that enables each DC-DC regulator as shown in Figure 1.
