资 源 简 介
These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for mulTIplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transiTIon of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management funcTIons that can be performed with the octal bus transceivers and registers.
Output-enable () and direcTIon-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers.
