资 源 简 介
This book is on the IEEE Standard Hardware DescripTIon Languagebased on the Verilog® Hardware DescripTIon Language (Verilog HDL),IEEE Std 1364–2001. The intended audiences are engineers involved invarious aspects of digital systems design and manufacturing and studentswith the basic knowledge of digital system design. The emphasis of thebook is on using Verilog HDL for the design, verificaTIon, and synthesis ofdigital systems. We will discuss Register Transfer (RT) level digital systemdesign, and discuss how Verilog can be used in this design flow.In the last few years RT level design of digital systems has gonethrough significant changes. Beyond simulaTIon and synthesis that arenow part of any RTL design process, we are looking at testbench generationand automatic verification tools. As with any book on Verilog,this book covers digital design and Verilog for simulation and synthesis.However, to ready design engineers for designing, testing, and verifyinglarge digital system designs, the book contains material fortestbench development and verification. The subjects of testbench andverification are introduced in Chapter 1. Chapter 2 onwards we concentrateon Verilog for design and synthesis. This will teach the readersefficient Verilog coding techniques for describing actual hardwarecomponents. When all of Verilog from a design point of view is presented,we turn our attention to test and verification. Chapter 6 coverstestbench development techniques and use of assertion verification monitorsfor better analysis of a design. Toward the end of the book we puttogether our coding techniques for synthesis and testbench development,and present several RT level designs from design specification toverification.
