tl16c550 pdf

The TL16C550A is a funcTIonal upgrade of the TL16C450 asynchronous communicaTIons element (ACE).FuncTIonally idenTIcal to the TL16C450 on power up (character mode†), the TL16C550A can be placed in analternate mode (FIFO) to relieve the CPU of excessive software overhead.In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiverFIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize systemefficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N packageand terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address(DMA) transfers.The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modemand parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status ofthe ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operationin progress, the status of the operation, and any error conditions encountered.The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable ofdividing a reference clock input by divisors from 1 to (216 –1) and producing a 16× clock for driving the internaltransmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in theACE is a complete modem control capability and a processor interrupt system that may be software tailoredto the user’s requirements to minimize the computing required to handle the communications link.