资 源 简 介
These triple 3-input posiTIve-AND gates are designed for 2-V to 5.5-V VCC operaTIon.
The ’LV11A devices perform the Boolean funcTIon Y = A • B • C or Y = (A + B + C) in posiTIve logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.