资 源 简 介
The SN74LVC257A quadruple 2-line to 1-line data selector/mulTIplexer is designed for 2.7-V to 3.6-V VCC operaTIon.
The device is designed for high-performance memory-decoding or data-rouTIng applicaTIons requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines.
