Design Recipes for FPGAs

This book is designed to be a desktop reference for engineers, studentsand researchers who use Field Programmable Gate Arrays(FPGA) as their hardware platform of choice. This book has beenproduced in the spirit of the ‘numerical recipe’ series of books forvarious programing languages – where the intention is not to teachthe language per se, but rather the philosophy and techniquesrequired, making your application work. The rationale of this bookis similar in that the intention is to provide the methods and understandingto make the reader able to develop practical, operationalVHDL that will run correctly on FPGAs.It is important to stress that his book is not designed as a languagereference manual for VHDL. There are plenty of thoseavailable and I have referenced them throughout the text. Thisbook is intended as a reference for design with VHDL and can beseen as complementary to a conventional VHDL textbook.ContentsAcknowledgements xviiPreface xixList of Figures xxiPart 1 Overview 1Chapter 1 Introduction 3Why FPGAS? 3Chapter 2 An FPGA Primer 5Introduction 5FPGA evolution 5Programmable logic devices 6Field programmable gate arrays 6FPGA design techniques 10Design constraints using FPGAs 10Summary 10Chapter 3 A VHDL Primer: The Essentials 11Introduction 11Entity: model interface 12Entity definition 12Ports 13Generics 13Constants 14Entity examples 14Architecture: model behavior 14Basic definition of an architecture 14Architecture declaration section 15Architecture statement section 15Process: basic functional unit in VHDL 16Basic variable types and operators 17Constants 17Signals 17Variables 18Boolean operators 18Arithmetic operators 18Comparison operators 19Shifting functions 19Concatenation 19Decisions and loops 20If-then-else 20Case 21For 21While and loop 22Exit 22Next 22Hierarchical design 23Functions 23Packages 23Components 24Procedures 25Debugging models 26Assertions 26Basic data types 26Basic types 26Data type: BIT 26Data type: Boolean 27Data type: integer 27Integer subtypes: natural 27Integer subtypes: positive 27Data type: character 27Data type: real 28Data type: time 28Summary 28Chapter 4 Design Automation and Testing for FPGAs 30Simulation 30Test benches 30Test bench goals 30Simple test bench: instantiating components 31Adding stimuli 32Libraries 33Introduction 33Using libraries 34Std_logic libraries 35Std_logic type definition 35Synthesis 36Design flow for synthesis 36Synthesis issues 38RTL design flow 38Physical design flow 39Place and route 40Recursive cut 40Timing analysis 40Design pitfalls 40VHDL issues for FPGA design 41Initialization 41Floating point numbers and operations 41Summary 41Part 2 Applications 43Chapter 5 Images and High-Speed Processing 45Introduction 45The camera link interface 46Hardware interface 46Data rates 47The Bayer pattern 47Memory requirements 48Getting started 49Specifying the interfaces 51Defining the top level design 51System block definitions and interfaces 52Overall system decomposition 52Mouse and keyboard interfaces 52Memory interface 53The display interface: VGA 53The cameralink interface 54The PC interface 55Summary 56Chapter 6 Embedded Processors 57Introduction 57A simple embedded processor 57Embedded processor architecture 57Basic instructions 59Fetch execute cycle 61Embedded processor register allocation 62A basic instruction set 62Structural or behavioral? 65Machine code instruction set 65Structural elements of the microprocessor 66Processor functions package 67The PC 68The IR 69The Arithmetic and Logic Unit 71The memory 72Microcontroller: controller 74Summary of a simple microprocessor 78Soft core processors on an FPGA 78Summary 79Part 3 Designer’s Toolbox 81Chapter 7 Serial Communications 83Introduction 83Manchester encoding and decoding 83NRZ coding and decoding 87NRZI coding and decoding 87RS-232 89Introduction 89RS-232 baud rate generator 89RS-232 receiver 90Universal Serial Bus 93Summary 96Chapter 8 Digital Filters 97Introduction 97Converting S-domain to Z-domain 98Implementing Z-domain functions in VHDL 100Introduction 100Gain block 100Sum and difference 101Division model 102Unit delay model 104Basic low pass filter model 105FIR filters 108IIR filters 109Summary 109Chapter 9 Secure Systems 110Introduction to block ciphers 110Feistel lattice structures 110The Data Encryption Standard 113Introduction 113DES VHDL implementation 115Validation of DES 121Advanced Encryption Standard 121Implementing AES in VHDL 126Summary 139Chapter 10 Memory 140Introduction 140Modeling memory in VHDL 141Read Only Memory 141Random Access Memory 143Synchronous RAM 145FLASH memory 147Summary 149Chapter 11 PS/2 Mouse Interface 150Introduction 150PS/2 mouse basics 150PS/2 mouse commands 151PS/2 mouse data packets 151PS/2 operation modes 151PS/2 mouse with wheel 152Basic PS/2 mouse handler VHDL 152Modified PS/2 mouse handler VHDL 153Summary 155Chapter 12 PS/2 Keyboard Interface 156Introduction 156PS/2 keyboard basics 156PS/2 keyboard commands 157PS/2 keyboard data packets 157PS/2 keyboard operation modes 157Basic PS/2 keyboard handler VHDL 157Modified PS/2 keyboard handler VHDL 158Summary 160Chapter 13 A Simple VGA Interface 161Introduction 161Basic pixel timing 162Image handling 162VGA interface VHDL 162Horizontal sync 164Vertical sync 165Horizontal and vertical blanking pulses 166Calculating the correct pixel data 167Summary 168Part 4 Optimizing Designs 169Chapter 14 Synthesis 171Introduction 171VHDL supported in RTL synthesis 172Initial conditions 172Concurrent edges 172Numeric types 173Wait statements 173Assertions 174Loops 174Some interesting cases where synthesis may fail 174What is being synthesized? 175Overall design structure 175Controller 175Data path 177Summary 178Chapter 15 Behavioral Modeling in VHDL 179Introduction 179How to go from RTL to behavioral VHDL 179Summary 183Chapter 16 Design Optimization 184Introduction 184Techniques for logic optimization 184Improving performance 186Critical path analysis 187Summary 188Chapter 17 VHDL-AMS 189Introduction 189Introduction to VHDL-AMS 190Analog pins: TERMINALS 191Mixed-domain modeling 192Analog variables: quantities 193Simultaneous equations in VHDL-AMS 194A VHDL-AMS example 194A DC voltage source 194Resistor 195Differential equations in VHDL-AMS 196Mixed-signal modeling with VHDL-AMS 197A basic switch model 201Basic VHDL-AMS comparator model 202Multiple domain modeling 204Summary 205Chapter 18 Design Optimization Example: DES 207Introduction 207The DES 207Moods 208Initial design 208Introduction 208Overall structure 208Data transformations 211Key transformations 213Initial synthesis 214Optimizing the data path 215Optimizing the key transformations 217Final optimization 218Results 219Triple DES 219Introduction 219Minimum area: iterative 220Minimum latency: pipelined 222Comparing the approaches 223Summary 224Part 5 Fundamental Techniques 225Chapter 19 Counters 227Introduction 227Basic binary counter 227Synthesized simple binary counter 230Shift register 233The Johnson counter 234BCD counter 236Summary 237Chapter 20 Latches, Flip-Flops and Registers 238Introduction 238Latches 238Flip-flops 240Registers 243Summary 244Chapter 21 Serial to Parallel & Parallel to Serial Conversion 245Serial to Parallel Conversion 245Parallel to Serial Conversion 246Summary 247Chapter 22 ALU Functions 248Introduction 248Logic functions 2481-bit adder 251Structural n-bit addition 252Configurable n-bit addition 253Twos complement 254Summary 257Chapter 23 Decoders and Multiplexers 258Decoders 258Multiplexers 260Summary 262Chapter 24 Finite State Machines in VHDL 263Introduction 263State transition diagrams 263Implementing FSM in VHDL 264Summary 265Chapter 25 Fixed Point Arithmetic in VHDL 266Introduction 266Basic fixed point types 268Fixed point functions 269Fixed-point to std_logic_vector functions 269Fixed point to real conversion 271Testing the fixed point function 272Summary 274Chapter 26 Binary Multiplication 275Introduction 275Basic binary multiplication 275VHDL unsigned multiplier 276Synthesis of the multiplication function 279‘Simple’ multiplication 280Summary 282Chapter 27 Bibliography 283Introduction 283Useful texts for VHDL 283Digital Systems Design 283Designers Guide to VHDL 283VHDL: Analysis and Modeling of Digital Systems 284VHDL for Logic Synthesis 284Useful Texts for FPGAs 284Design Warriors Guide to FPGAs 284General Digital Design Books 284Digital Design 284Index 287