首页| 行业标准| 论文文档| 电子资料| 图纸模型
购买积分 购买会员 激活码充值

您现在的位置是:团子下载站 > 通信网络 > 基于NXP ARM微控制器的以太网吞吐量

基于NXP ARM微控制器的以太网吞吐量

  • 资源大小:0.53 MB
  • 上传时间:2021-08-07
  • 下载次数:0次
  • 浏览次数:47次
  • 资源积分:1积分
  • 标      签: 以太网 arm 微控制器

资 源 简 介

基于NXP ARM微控制器的以太网吞吐量   本文提出了一种测量以太网吞吐量的方法,提供了良好的性能估计,并说明了影响性能的各种因素。   以太网是世界上应用最广泛的局域网(LAN)技术。它从80年代初开始使用,并被IEEE STD 802.3所覆盖,它指定了许多速度等级。在嵌入式系统中,最常用的格式是10 Mbps和100 Mbps(通常称为10/100以太网)。   有超过20的NXP ARM MCU内置以太网,涵盖所有三代(ARM7、ARM9、ARM的Cortex-M3)。恩智浦使用基本相同的实现跨越三代,使设计人员可以利用他们的以太网功能,当系统进入ARM的下一代节省时间和资源。   本文讨论了三种不同的情况下测量以太网吞吐量的LPC1700产品和细节,真正实现了优化系统。     Superior implementaTIon   NXP‘s Ethernet block (see Figure 1) contains a full-featured 10/100 Ethernet MAC (media access controller) which uses DMA hardware acceleraTIon to increase performance. The MAC is fully compliant with IEEE Std 802.3 and interfaces with an off-chip Ethernet PHY (physical layer) using the Media Independent Interface (MII) or Reduced MII (RMII) protocol along with the on-chip MII Management (MIIM) serial bus.   The NXP Ethernet block is disTInguished by the following:   Full Ethernet funcTIonality — The block supports full Ethernet operation, as specified in the 802.3 standard.   Enhanced architecture — NXP has enhanced the architecture with several additional features including receive filtering, automatic collision back-off and frame retransmission, and power management via clock switching.   DMA hardware acceleration — The block has two DMA managers, one each for transmit and receive. Automatic frame transmission and reception with Scatter-Gather DMA offloads the CPU even further.
VIP VIP