资 源 简 介
The SN65LVDS315 is a camera serializer that converts 8-bit parallel camera data into MIPI-CSI1 or SMIA CCP compliant serial signals.
The device converts the parallel 8-bit data to two sub-low-voltage differenTIal signaling (SubLVDS) serial data and clock output. The parallel data is latched in with the pixel clock input DCLK on the falling clock edge. The control inputs VS and HS are used to determine line and frame synchronizaTIon.
The serialized data is presented on the differenTIal serial data output DOUT with a differenTIal clock signal on output CLK. The frequency of CLK is 8× the DCLK input pixel clock rate.
Flexible printed circuit (FPC) cabling typically interconnects the SN65LVDS315 with the CSI-1 compliant receiver.
